Aeluros Overview
Aeluros is a fabless semiconductor company innovating serial, high- performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of...More»
Aeluros is a fabless semiconductor company innovating serial, high- performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. Aeluros has also released to general availability three intellectual property cores addressing common physical-layer requirements in PCI Express, Serial ATA, and XAUI. These cores provide access to the Aeluros high speed links for systems or semiconductor companies in need of a physical layer solution in these rapidly growing marketplaces. All three cores are silicon validated and comply with Aeluros' stringent quality and performance standards.«Less
Key People
Management
Board of Directors
Funding
| Date | Type | Capital Amount | Post-Money Valuation | Investors |
|---|---|---|---|---|
| 10/03/2004 | Series B | 10M | Unknown |
Products
| Name: | Puma 10G PHY devices |
| Product URL: | http://www.aeluros.com/products.html |
| Description: | The Puma family of 10G PHY devices comprises single-channel CMOS physical layer transceiver devices that include the SerDes function [10G/XAUI] and provide full implementation of the PMA, PCS and XGXS sub-layers of the IEEE 802.3ae 10 Gigabit Ethernet and INCITS 10 Gigabit Fibre Channel standards. This includes implementation of: 10 Gbps and 3 Gbps clock and data recovery Serialization/deserialization 64B/66B and 8B/10B encoding/decoding Synchronization, alignment and deskew functions Line Side System Side Standard 10 Gigabit Ethernet 10.3125 Gbps 4 x 3.125 Gbps IEEE802.3ae 10 Gigabit Fibre Channel 10.51875 Gbps 4 x 3.1875 Gbps INCITS 10GFC 10 Gigabit Ethernet WIS 9.953 Gbps 4 x 3.125 Gbps IEEE 802.3ae The Puma devices exhibit jitter tolerance and jitter generation performance characteristics that substantially exceed specifications. In addition, the integration of a limiting amplifier provides a single-ended input receiver sensitivity of 10mV, allowing the flexibility to choose optical components based upon price and power considerations. The XAUI interface is capable of driving 3.125 Gbps signals across 40 inches of FR-4 backplane. Aeluros has developed 2 families of 10G PHY products specially focused on two different application segments: Optimized for XAUI-based optical modules (power and MDIO optimized) Optimized for line-card applications (includes adaptive equalizer for optimizing FR4 distance between PHY and XFP) Application Characteristic Aeluros Solution Low Power LAN PHY Optimized for 10GBASE-R modules Puma AEL1001 Low Latency LAN PHY Optimized for data center clustering Puma AEL1002 Low Power LAN PHY Optimized for 10GBASE-LRM modules Puma AEL1003 Low Power LAN/WAN PHY Optimized for 10GBASE-R & -W modules Puma AEL1004 Low Power LAN/WAN PHY Optimized for 10GBASE-R & -W line cards Puma AEL1005 LAN PHY with VCSEL driver Optimized for 10GBASE-SR modules Puma AEL1006 |
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