Azuro

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Headline: Clock implementation for nanometer design

Website: http://www.azuro.com/

Azuro is a provider of electronic design automation (EDA) software for digital semiconductor chip design. Azuro's unique technology enables electronics companies around the world to implement digital clock networks with significantly less manual effort and with significantly lower power consumption than ever before.

Azuro's software is being used by leading semiconductor companies around the...More»

Address: 5201 Great America Parkway Suite 432 Santa Clara, CA 95054 Map it »

Phone: 408-970-8200

Email: info@azuro.com

Founded: 2002

Industry: Software

Sub-Industry: Business Application

Legal Structure: Corporation

Ownership: Private

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Management

Board of Directors

Date	Type	Capital Amount	Post-Money Valuation	Investors
12/31/2007	Series B	13M	Unknown	Benchmark Capital, Cambridge Angels, Miramar Venture Partners, TTP Ventures

Name:	Azuro PowerCentric
Product URL:	http://www.azuro.com/prod/prod01.htm
Description:	Azuro's PowerCentric solution delivers a complete multi-objective clock implementation capability to the designer, slotting seamlessly into the design flow as a complete replacement for CTS and post-CTS optimization. Unlike traditional CTS solutions, PowerCentric directly considers the impact of clock tree buffering and clock gating on power, congestion, and setup and hold timing across multiple modes and corners. It can completely restructure the clock tree in a design, delivering a routable, aggressively gated, extremely low buffer count clock tree which meets setup and hold timing across multiple modes and corners in the presence of OCV derates. Reduced power * Significantly less clock tree buffer and wire capacitance * Additional clock gating above and below RTL clock gating * True optimization for lowest cap x freq not just lowest cap Improved variability management * Control clock skew concurrently across multiple corners * Concurrent multi-corner hold fixing * Concurrent multi-corner aware useful skew Enhanced timing closure * Timing aware clock gate hierarchy restructuring * Integrated timing optimization for clock gate enable logic * Multi-stage useful skew for setup and hold with OCV derates Increased productivity * Reduced flow iterations between CTS and post-CTS optimization * Eliminate the need for complex clock tree configuration scripts * Understand complex clock structures quickly with unique GUI Timing Analysis * Built-in static timing engine with full SDC support * Excellent correlation with 3rd party sign-off tools * Setup and hold timing analysis * OCV derates and CPPR Power Analysis * Full chip dynamic and leakage power reporting * VCD, SAIF, TCF import * Fully vectorless statistical average-case activity estimation Variability Analysis * Concurrent multi-mode timing analysis* * Concurrent multi-corner timing analysis* * Concurrent multi-mode power analysis * Full MSV support with CPF/UPF roadmap* Placement and logic optimization * Congestion and timing aware global placement and legalization * Cell sizing and logic re-structuring * High fanout net synthesis * Multi-corner hold fix buffer insertion* Global routing * Advanced statistical track and metal layer assignment * Wire caps estimated based on 3D field solver * Supports shielding, variable spacing, and load-based routing rules Clock tree balancing * Global skew and useful skew** modes * Complex clock tree routing rule support * Automatic balancing of complex muxed-clock configurations * Concurrent multi-corner skew minimization* * Clock tree balancing between voltage islands* Additional gate level clock gate enable synthesis*** * Above and beyond front-end clock gating * Placement, timing, congestion, and activity aware Powerful GUI with advanced synthesis capabilites * Topological and physical clock tree views * Full cross-probing capabilites between all views * Fully Tcl scriptable design environment and data model Easy integration with mainstream EDA design flows * Flat and hierarchical netlist import and export * Compatible with formal equivalence checkers and design-for-test tools
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